View ICS9248-157_26372.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9248-157
Frequency Timing Generator for Pentium II Systems
Recommended Application: ALI1621/1632M style chipsets Output Features: * 2 - CPUs @2.5V, up to 140MHz. * 7 - PCI @3.3V, (including one free running) * 1 - 48MHz, @3.3V fixed. * 2 - REF @3.3V, 14.318MHz. Features: * Up to 140 MHz frequency support * Support power management: CPU, PCI stop and Power down. * Spread spectrum for EMI control (0.5% down spread). * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU - CPU: <175ps * PCI - PCI: <250ps * CPU(early)-PCI: 1.5ns - 4ns * PCI_E (early) - PCI: 2.1ns
Pin Configuration
*FS1/REF0 X1 X2 **FS2/PCICLK_F *SEL_CPUF#/PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK_E VDD48 *FS3/48MHz
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDR REF1/FS0* SPREAD# VDDL CPUCLK1 CPUCLK0/F GNDL GND PCI_STOP# VDDA CPU_STOP# PD# DIV/4# GND
28 Pin 209mil SSOP
*These inputs have a 120K pull up to VDD **These inputs have a 120K pull down to GND
Block Diagram
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 33.33 63.33 69.99 66.66 97.00 96.22 91.50 83.33 50.00 95.25 105.00 100.00 66.66 126.35 139.65 133.33 PCI 16.66 31.66 35.00 33.33 32.33 32.07 30.50 27.77 16.66 31.75 35.00 33.33 16.66 31.66 35.00 33.33
X1 X2 CPU_STOP#
OSC
2
REF (1:0)
FS (3:0)
PLL Spread Spectrum Glitch Free Control Logic
/4
CPU STOP CPU STOP /2 /3 BUS STOP
2
CPUCLK 1 CPUCLK0/F
PD# Div4# SPREAD# SEL_CPUF#
5
PCICLK (4:0), PCICLK_E
PCI_STOP#
PCICLK_F
PLL2
48MHz
9248-157 Rev A - 1/16/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is
ICS9248-157
Advance Information
ICS9248-157
General Description
The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system. Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Descriptions
Pin number
1 2 3 4
Pin name
FS1 REF0 X1 X2 FS2 PCICLK_F SEL_CPUF# PCICLK0 PCICLK (4:1) GND VDDPCI PCICLK_E VDD48 FS3 48MHz DIV4# PD#
Type
Input Output Input Output Input Output Input Output Output Power Power Output Power Input Output Input Input Frequency select pin
Description
3.3V, 14.318 MHz reference clock output. 14.318 MHz crystal input 14.318 MHz crystal output Frequency select pin 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# Active low input to select CPUCLK0/F (pin 23) either normal CPUCLK or Free running (not stoppable through CPU_STOP#) clock. 3.3V PCI clock output 3.3 V PCI clock outputs, generating timing requirements Ground for clock outputs 3.3 V power for the PCI clock outputs Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP# 3.3 V power for 48 MHz clocks Frequency select pin Fixed 48MHz clock. Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular frequecies Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Asynchronous active low input pin used to stop the CPUCLK in active low state, all other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at least 3 CPU clocks. 3.3 V power for the core Synchronous active low input used to stop the PCICLK in active low state. It will not effect PCICLK_F or any other outputs. Ground for the CPU and Host clock outputs 2.5V CPU clock output; can be selected to be free running by driving SEL_CPUF# low 2.5 V CPU and Host clock outputs 2.5 V power for the CPU and Host clock outputs power-on spread spectrum enable option. Active low = spread spectrum clocking enable. Active high = spread spectrum clocking disable. Frequency select pin 3.3V, 14.318 MHz reference clock output. 3.3 V power for the REFCLK and crystal clock outputs
5 11, 10, 9, 6 7, 15, 21 8 12 13 14 16 17
18 19 20 22 23 24 25 26 27 28
CPU_STOP# VDDA PCI-STOP# GNDL CPUCLK0/F CPUCLK1 VDDL SPREAD# FS0 REF1 VDDR
Input Power Input Power Output 0utput Power Input Input Output Power
Third party brands and names are the property of their respective owners.
2
ICS9248-157
Power Management
Clock Enable Configuration
C P U _ S TO P # P C I _ S TO P # X X 0 0 0 1 1 0 1 1 P W R _ DW N # 0 1 1 1 1 CPUCLK L ow Low Low Running Running PCICLK L ow Low Running Low Running PCICLK_F L ow Running Running Running Running REF Stopped Running Running Running Running Crystal O ff Running Running Running Running VCOs O ff Running Running Running Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
Power Management Requirements
SIGNAL C P U _ S TO P # P C I _ S TO P # PD# SIGNAL STATE 0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1 1 (Normal Operation)3 0 (Power Down)4 L a t e n cy No. of rising edges of free running PCICLK 1 1 1 1 3ms 2max
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device. 3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device. 4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF will be stopped independant of these.
Power Groups:
VDDA = PLL Core VDD48 = 48MHz Core VDDPCI = PCICLK VDDL = CPUCLK VDDR = Xtal & REF
Third party brands and names are the property of their respective owners.
3
Advance Information
ICS9248-157
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD+0.3 V Input Low Voltage VIL VSS-0.3 0.8 V Input High Current IIH VIN = VDD 0.1 5 A VIN = 0 V; Inputs with no pull-up resistors -5 2.0 Input Low Current IIL1 A VIN = 0 V; Inputs with pull-up resistors -200 -100 Input Low Current IIL2 A 60 180 mA Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz 66 180 mA Power Down IDD3.3PD CL = 0 pF; With input address to Vdd or GND 70 600 A Supply Current Input frequency Fi VDD = 3.3 V; 11 14.318 16 MHz Input Capacitance1 CIN Logic Inputs 5 pF CINX X1 & X2 pins 27 36 45 pF Transition Time1 Ttrans To 1st crossing of target Freq. 3 ms Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq. 3 ms Skew1 TCPU-PCI1 VT = 1.5 V; 1.5 2.3 4 ns
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Operating IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz 16 CL = 0 pF; Select @ 100 MHz 23 Supply Current IDD2.5OP100 Skew1 tCPU-PCI2 VT = 1.5 V; VTL = 1.25 V 1.5 3
1
MAX 72 100 4
UNITS mA mA ns
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
4
ICS9248-157
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH2B IOH = -12.0 mA 2 IOL = 12 mA Output Low Voltage VOL2B VOH = 1.7 V Output High Current IOH2B Output Low Current IOL2B VOL = 0.7 V 19 1 VOL = 0.4 V, VOH = 2.0 V Rise Time tr2B VOH = 2.0 V, VOL = 0.4 V Fall Time tf2B1 1 VT = 1.25 V 45 Duty Cycle dt2B 1 VT = 1.25 V Skew tsk2B Jitter, Cycle-to-cycle tjcyc-cyc2B1 VT = 1.25 V VT = 1.25 V Jitter, One Sigma tj1s2B1 1 tjabs2B VT = 1.25 V Jitter, Absolute -250
1
TYP 2.3 0.2 -41 37 0.99 1.05 50.3 34 203
MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55 % 175 ps 250 ps 150 ps +250 ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5% VDDL = 2.5 V +/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage VOL1 IOL = 9.4 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V Rise Time Fall Time
1 1
MIN 2.4
16
TYP 3.1 0.1 -62 57 1.5 1.1
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 500 150 ns ns % ps ps ps ps
tr1 tf1 dt1 tsk1 tjcyc-cyc1 tj1s1 tjabs1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.25 V VT = 1.5 V VT = 1.5 V -250 45
1 1
Duty Cycle
50 290 200
Skew Jitter, Cycle-to-cycle Jitter, One Sigma 1 Jitter, Absolute
1 1
250
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
Advance Information
ICS9248-157
Electrical Characteristics - REF/48MHz
TA = 0 - 70C; VDDL= 2.5V+/-5%; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH5 IOH = -12 mA 2.6 Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 16 Rise Time1 Fall Time
1 1 1
TYP 3.1 0.17 -44 42 1.03 0.9
MAX UNITS V 0.4 V -22 mA mA 4 4 55 3 5 ns ns % % %
tr5 tf5 dt5 tj1s5 tjabs5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45
Duty Cycle
52.9
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-157
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248157 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
7
Advance Information
ICS9248-157
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9248-157. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9248-157. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
8
ICS9248-157
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-157. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-157 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
9
Advance Information
ICS9248-157
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal is synchronized internally by the ICS9248-157 prior to its control action of powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are don't care signals during the power down operations.
CPUCLK (Internal) PCICLK (Internal) PD#
CPUCLK PCICLK_E, PCICLK_F, PCICLK REF INTERNAL VCOs INTERNAL CRYSTAL OSC.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
Third party brands and names are the property of their respective owners.
10
ICS9248-157
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 0.05 1.65 0.22 2.00 1.85 0.38
In Inches COMMON DIMENSIONS MIN MA X .002 .065 .009 .079 .073 .015
A A1 A2 b c D E E1 e L N V A RIA TIONS N 28
0.09 0.25 SEE V A RIA TIONS 7.40 8.20 5.00 5.60 0.65 BA SIC 0.55 0.95 SEE V A RIA TIONS 0 8
.0035 .010 SEE V A RIA TIONS .291 .323 .197 .220 0.0256 BA SIC .022 .037 SEE V A RIA TIONS 0 8
D mm. MIN 9.90 MA X 10.50 MIN .390
D (inch) MA X .413
6 / 1/ 0 0 R ev B
M O-1 5 0 J E D E C D oc . # 1 0 -0 0 33
Ordering Information
ICS9248yF-157-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
11
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is

▲Up To Search▲

Price & Availability of ICS9248-157

	To Download ICS9248-157 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .